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PD -94835
IRFIZ48NPBF
l l l l l l
Advanced Process Technology Isolated Package High Voltage Isolation = 2.5KVRMS Sink to Lead Creepage Dist. = 4.8mm Fully Avalanche Rated Lead-Free
HEXFET(R) Power MOSFET VDSS = 55V RDS(on) = 0.016
D
G S
ID = 40A
Description
Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The TO-220 Fullpak eliminates the need for additional insulating hardware in commercial-industrial applications. The moulding compound used provides a high isolation capability and a low thermal resistance between the tab and external heatsink. This isolation is equivalent to using a 100 micron mica barrier with standard TO-220 product. The Fullpak is mounted to a heatsink using a single clip or by a single screw fixing. Parameter
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 srew
TO-220 FULLP AK
Absolute Maximum Ratings
Max.
40 29 210 54 0.36 20 270 32 5.4 5.0 -55 to + 175 300 (1.6mm from case ) 10 lbfin (1.1Nm)
Units
A W W/C V mJ A mJ V/ns C
Thermal Resistance
Parameter
RJC RJA Junction-to-Case Junction-to-Ambient
Typ.

Max.
2.8 65
Units
C/W
11/13/03
IRFIZ48NPBF
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
V(BR)DSS
V(BR)DSS/TJ
RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss C
Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Drain to Sink Capacitance
Min. 55 2.0 22
Typ. 0.052 11 78 32 48 4.5 7.5 1900 620 270 12
Max. Units Conditions V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 1mA 0.016 VGS = 10V, ID = 22A 4.0 V VDS = VGS, ID = 250A S VDS = 25V, ID = 32A 25 VDS = 55V, VGS = 0V A 250 VDS = 44V, VGS = 0V, TJ = 150C 100 VGS = 20V nA -100 VGS = -20V 89 ID = 32A 20 nC VDS = 44V 39 VGS = 10V, See Fig. 6 and 13 VDD = 28V ID = 32A ns RG = 5.1 RD = 0.85, See Fig. 10 Between lead, 6mm (0.25in.) nH G from package and center of die contact VGS = 0V VDS = 25V pF = 1.0MHz, See Fig. 5 = 1.0MHz
D
S
Source-Drain Ratings and Characteristics
IS
I SM
VSD t rr Q rr Notes:
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge
Min. Typ. Max. Units 94 360 49 A 210 1.3 140 540 V ns nC
Conditions MOSFET symbol showing the G integral reverse p-n junction diode. TJ = 25C, IS = 22A, VGS = 0V TJ = 25C, IF = 32A di/dt = 100A/s
D
S
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Pulse width 300s; duty cycle 2%. t=60s, =60Hz
Uses IRFZ48N data and test conditions
VDD = 25V, starting TJ = 25C, L = 530H
RG = 25, IAS = 32A. (See Figure 12)
ISD 32A, di/dt 250A/s, VDD V(BR)DSS,
T J 175C
IRFIZ48NPBF
1000
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
1000
I , Drain-to-Source Current (A) D
I , Drain-to-Source Current (A) D
100
100
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
10
10
4.5V
1
1
4.5V
0.1 0.1 1
20s PULSE WIDTH TC = 25C
10
A
100
0.1 0.1
20s PULSE WIDTH TC = 175C
1 10 100
A
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
2.5
R DS(on) , Drain-to-Source On Resistance (Normalized)
I D = 53A
I D , Drain-to-Source Current (A)
2.0
100
TJ = 175C
10
1.5
TJ = 25C
1.0
1
0.5
0.1 4 5 6 7
V DS = 25V 20s PULSE WIDTH
8 9 10
A
0.0 -60 -40 -20 0 20 40 60
VGS = 10V
80 100 120 140 160 180
A
VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
IRFIZ48NPBF
4000
C, Capacitance (pF)
3000
Ciss
2000
Coss
V GS , Gate-to-Source Voltage (V)
V GS = 0V, f = 1MHz C iss = Cgs + C gd , Cds SHORTED C rss = C gd C oss = C ds + C gd
20
I D = 32A V DS= 44V V DS= 28V
16
12
8
1000
Crss
4
0 1 10 100
A
0 0 20 40
FOR TEST CIRCUIT SEE FIGURE 13
60 80 100
A
VDS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000
1000
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY RDS(on)
TJ = 175C
10
ID , Drain Current (A)
100
10us
100 100us
TJ = 25C
10
1ms
1
10ms
0.1 0.2 0.6 1.0 1.4 1.8
VGS = 0V
2.2
A
1
TC = 25 C TJ = 175 C Single Pulse
1 10 100
2.6
VSD , Source-to-Drain Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
IRFIZ48NPBF
VDS
50
RD
V GS RG
D.U.T.
+
40
-V DD
ID , Drain Current (A)
10V
30
Pulse Width 1 s Duty Factor 0.1 %
20
Fig 10a. Switching Time Test Circuit
VDS 90%
10
0
25
50
TC , Case Temperature ( C)
75
100
125
150
175
10% VGS
td(on) tr t d(off) tf
Fig 9. Maximum Drain Current Vs. Case Temperature
10
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
D = 0.50 1 0.20 0.10 0.05 0.1 0.02 0.01 PDM t1 SINGLE PULSE (THERMAL RESPONSE) t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.001 0.01 0.1 1 10
0.01 0.00001
0.0001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
IRFIZ48NPBF
E AS , Single Pulse Avalanche Energy (mJ)
700
15V
TOP
600
BOTTOM
ID 13A 22A 32A
VDS
L
DRIVER
500
RG
20V
D.U.T
IAS tp
+ - VDD
400
A
300
0.01
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS tp
200
100
0
VDD = 25V
25 50 75 100 125 150
A
175
Starting TJ , Junction Temperature (C)
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
50K
QG
12V
.2F .3F
10 V
QGS VG QGD
VGS
3mA
D.U.T.
+ V - DS
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
IRFIZ48NPBF
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS
IRFIZ48NPBF
TO-220 Full-Pak Package Outline
TO-220 Full-Pak Part Marking Information
E XAMP L E : T H IS IS AN IR F I84 0G WIT H AS S E MB L Y L OT CODE 3432 AS S E MB L E D ON WW 24 1999 IN T H E AS S E MB L Y L INE "K " IN T E R NAT IONAL R E CT IF IE R L OGO AS S E MB L Y L OT CODE P AR T N U MB E R
IR F I8 40G 924 K 34 32
Note: "P" in assembly line position indicates "Lead-Free"
DAT E COD E YE AR 9 = 1999 WE E K 24 L IN E K
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.11/03
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/

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